The complete flow, hands-on
Digital: RTL to GDSII. Analog: specification to GDSII. Every stage on open-source tools you keep using after the internship, with exposure to the commercial tools industry uses.
December 2026 batch starts 10 December · Apply by 25 November 2026
6-Month VLSI Design & Tape-out Internship
Choose your track: Digital VLSI or Analog & Mixed-Signal.
A hands-on internship for B.Tech students. Learn the complete chip-design flow on open-source EDA tools (with exposure to the commercial tools industry uses), build a capstone design of your own, and take it to a tape-out-ready layout — with the option to fabricate it on GF180MCU or UMC65 through the Vidyutt Academic Chip Shuttle (VACS).
- 2 tracksDigital VLSI or Analog & Mixed-Signal
- 10 Dec 2026batch starts · apply by 25 Nov
- ₹50,000programme fee per student, either track
- Real siliconoptional VACS tape-out on GF180MCU or UMC65
Why this internship
Go beyond simulation — take a design to silicon
Most VLSI courses stop at simulation or an FPGA demo. Industry hires engineers who have closed timing, matched a layout, fixed DRC violations and signed off a real design. This internship takes you through every stage of the chip-design flow on a single design of your own — and ends with a tape-out-ready layout you can send to the fab.
Your own chip
Take your capstone design to silicon through the Vidyutt Academic Chip Shuttle (VACS) on GF180MCU or UMC65, and receive packaged chips for testing. Tape-out is optional and charged per tile.
Projects that matter
Capstone themes in AI/ML hardware, neuromorphic computing, power management, sensor interfaces, cryptography and hardware security.
Mentored by practitioners
Weekly design reviews and signoff reviews with engineers who run the VACS tape-out flow.
A portfolio that proves it
Graduate with a GDSII of your own design, simulation and signoff reports, your design files on Git and, if you fabricate, a VACS tape-out record — evidence that recruiters and graduate schools can verify.
Choose your track
One fee, two ways to build a chip
Both tracks run for six months, follow the same weekly rhythm, include the same mentorship and certification, and end in a tape-out-ready design. You choose your track on the application form.
Track A
Digital VLSI Design (RTL-to-GDSII)
- Verilog RTL, SystemVerilog / UVM verification
- Synthesis, timing analysis and physical design
- Signoff and tape-out package
- Capstones: crypto cores, AI accelerators, RISC-V
Best for: students who enjoy coding, logic design and architecture.
Track A in detailTrack B
Analog & Mixed-Signal Design
- Transistor-level circuit design and simulation
- Custom layout, matching and physical verification
- Parasitic extraction and post-layout analysis
- Capstones: bandgap/LDO, op-amps, ADCs, analog AI
Best for: students who enjoy circuits, devices and analog electronics.
Track B in detail| Track A · Digital | Track B · Analog & Mixed-Signal | |
|---|---|---|
| Duration | 6 months (26 weeks) | 6 months (26 weeks) |
| Total hours | ~444 (≈ 200 on the capstone) | ~444 (≈ 200 on the capstone) |
| Learning modules | 10 modules, weeks 1–15 | 8 modules, weeks 1–11 |
| Key open-source tools | Icarus, Verilator, cocotb, Yosys, OpenSTA, OpenROAD / OpenLane | Xschem, ngspice, Magic, Netgen, KLayout |
| Key commercial tools | Synopsys VCS / DC / PrimeTime, Cadence Innovus, Siemens Calibre | Cadence Virtuoso & Spectre, Siemens Calibre |
| Recommended background | Digital logic; basic C or Python | Analog electronics / network theory; basic C or Python |
| Programme fee | ₹50,000 | ₹50,000 |
| Optional tape-out intern rate | ₹35,000 per tile | ₹35,000 per tile |
Track A
Digital VLSI Design (RTL-to-GDSII)
From Verilog to a signed-off layout, on one design of your own
Weeks 1–15 build skills module by module. From week 8 the capstone project starts and runs alongside, so every new skill is applied immediately to your own design.
Month by month
- Month 1RTL design
- Month 2Verification
- Month 3Synthesis & STA
- Month 4Physical design
- Month 5Signoff
- Month 6Tape-out package
- OptionalPackaged chip
Learning modules
| When | Module | What you learn | Open-source tools | Commercial tools |
|---|---|---|---|---|
| Wk 1 | Digital IC & CMOS foundations | MOS transistor, CMOS gates, delay & logical effort, power, sequential timing (setup/hold, skew), datapath & memory basics | ngspice, Magic | Cadence Virtuoso, Spectre / HSPICE |
| Wk 1–2 | Linux, Git, TCL & Python for EDA | Shell, Vim, Git, Makefiles; TCL procs and file handling; Python for log parsing, test vectors and golden models | Linux, Git, TCL, Python | TCL shells of Synopsys / Cadence tools |
| Wk 2–4 | Verilog HDL & RTL design | Synthesizable Verilog, FSMs, memories, FIFOs, parameterised code, clock/reset & CDC design, APB / AXI-Lite interfaces | Icarus, Verilator, GTKWave | Synopsys VCS, Cadence Xcelium, Synopsys SpyGlass (lint/CDC) |
| Wk 5–7 | Functional verification | SystemVerilog testbenches, constrained random, functional & code coverage, SVA assertions, cocotb, UVM essentials, formal basics | Verilator, cocotb, SymbiYosys | VCS / Xcelium / Questa with UVM, Synopsys Verdi, Cadence JasperGold |
| Wk 7–8 | Hardware for AI & crypto | Pipelining, retiming, folding, systolic arrays, INT8 quantised arithmetic, modular & GF(2ⁿ) arithmetic | Python + RTL | MATLAB / Simulink, Siemens Catapult HLS |
| Wk 9 | Logic synthesis & LEC | Liberty/LEF inputs, synthesis flow, optimisation, scan insertion basics, netlist qualification, equivalence checking | Yosys, ABC, eqy | Synopsys Design Compiler / Cadence Genus, Synopsys Formality / Cadence Conformal |
| Wk 10 | Static timing analysis & SDC | Timing paths, clocks, generated/virtual clocks, exceptions, multi-corner analysis, OCV and signal integrity | OpenSTA | Synopsys PrimeTime, Cadence Tempus |
| Wk 11–13 | Physical design (RTL → GDSII) | Floorplan, IO & power planning, placement, CTS, routing, ECO, design-space exploration | OpenROAD, OpenLane 2 | Cadence Innovus, Synopsys ICC2 / Fusion Compiler |
| Wk 14 | Signoff | Extraction, multi-corner STA, DRC / LVS / antenna / density, IR drop, gate-level simulation with SDF | Magic, KLayout, Netgen, OpenSTA | Siemens Calibre, Synopsys StarRC, Cadence Voltus / Ansys RedHawk |
| Wk 15 | PDK & VACS tape-out flow | GF180MCU layers, cells and IO; VACS tile and harness, pre-check, tape-out documentation, bring-up planning; overview of the UMC65 tape-out route | GF180MCU PDK | UMC65 foundry PDK, Siemens Calibre |
Capstone project phases
| Phase | Weeks | Activity | Project hrs |
|---|---|---|---|
| P1 | Wk 8–9 | Specification, micro-architecture and PPA targets; tile-area budget | 12 |
| P2 | Wk 9–10 | Bit-accurate golden model (Python) and test vectors | 12 |
| P3 | Wk 10–14 | RTL implementation, lint-clean and CDC-clean | 40 |
| P4 | Wk 12–17 | Verification environment, regressions and coverage closure | 40 |
| P5 | Wk 16–20 | Synthesis, floorplan, placement, CTS, routing and timing closure | 40 |
| P6 | Wk 20–23 | Signoff: STA clean, DRC/LVS clean, IR within budget, gate-level simulation | 30 |
| P7 | Wk 23–25 | Tape-out package: harness integration, pre-check, GDSII ready for VACS submission | 16 |
| P8 | Wk 25–26 | Final report, design review presentation and viva | 10 |
| Project total | 200 | ||
Example capstone projects
Interns work individually or in teams of two to three on one capstone design, sized to fit one or more VACS silicon tiles — 300 µm × 300 µm on GF180MCU or 200 µm × 200 µm on UMC65.
PRESENT / ASCON lightweight cipher core
A round-based block cipher or authenticated-encryption core verified against NIST test vectors, optimised for minimum area.
Ring-oscillator PUF + true random number generator
A physical-unclonable-function for chip identity and an entropy source with online health tests — with hand-placed oscillators inside a digital flow.
INT8 systolic MAC array
A small systolic array for matrix multiply with requantisation, verified bit-exact against a NumPy model of a neural-network layer.
Binarised neural-network inference engine
An XNOR-popcount engine running a compact keyword-spotting or digit-recognition network, with on-chip weight memory.
Spiking-neuron (LIF) array
An event-driven leaky-integrate-and-fire neuron array with configurable weights — a low-power alternative to conventional neural-network hardware.
Bit-serial RISC-V core with crypto extension
A minimal-area RV32I core extended with custom instructions for AES or SHA rounds, running a C test program in gate-level simulation.
Note: The projects listed above are indicative only. Actual capstone projects may differ and are finalised with your mentor during the internship, based on your interests, mentor guidance and the silicon area available on the shuttle.
Skills you will build
- Write synthesizable, CDC-safe RTL
- Build self-checking testbenches with coverage and assertions
- Synthesise, write SDC and close timing
- Run floorplan, placement, CTS and routing
- Clear DRC, LVS and multi-corner STA signoff
- Automate EDA flows with TCL and Python
Track B
Analog & Mixed-Signal Design
From specification to a verified custom layout, on one design of your own
Weeks 1–11 build skills module by module. From week 9 the capstone project starts and runs alongside, so every new skill is applied immediately to your own circuit.
Month by month
- Month 1Circuit design & analysis
- Month 2Pre-layout verification
- Month 3Physical layout
- Month 4Physical verification
- Month 5Post-layout optimisation
- Month 6Signoff & documentation
Learning modules
| When | Module | What you learn | Open-source tools | Commercial tools |
|---|---|---|---|---|
| Wk 1–2 | IC design fundamentals & specification | The complete specification-to-GDSII flow; NMOS and PMOS I–V characteristics; exploring the selected PDK and its device libraries | Xschem, ngspice | Cadence Virtuoso |
| Wk 2–3 | Circuit architecture & transistor-level design | Designing and simulating basic CMOS circuits; analysing circuit performance; sizing transistors (gm/Id method) | Xschem, ngspice | Cadence Virtuoso, Spectre |
| Wk 4 | Schematic simulation & verification | Bias points and operating regions; DC, transient and AC analysis; PVT corners and Monte Carlo; design optimisation | ngspice | Cadence Virtuoso, Spectre / ADE |
| Wk 4–6 | Analog layout & physical implementation | Layers, design rules and layout-dependent effects; matching, symmetry and common-centroid layout; guard rings, substrate contacts, well taps and isolation; routing, parasitics, power and grounding | Magic, KLayout | Cadence Virtuoso Layout |
| Wk 7 | Physical verification | DRC, LVS and antenna checks; debugging and resolving verification errors | Magic, Netgen, KLayout | Siemens Calibre |
| Wk 8 | Parasitic extraction & post-layout analysis | Extracted netlists; post-layout simulation; comparing gain, bandwidth, delay and power with pre-layout results; re-checking specifications across corners | Magic, Netgen, ngspice | Siemens Calibre xRC / Quantus, Cadence Spectre |
| Wk 9–10 | Mixed-signal integration & verification | Analog–digital interfaces, digital control logic, top-level mixed-signal simulation, Verilog-A behavioural models | Xschem, ngspice, Icarus | Cadence Virtuoso AMS, Spectre AMS Designer |
| Wk 11 | Signoff & VACS tape-out flow | IO and ESD, pad-ring and harness connection, final DRC/LVS, documentation, GF180MCU and UMC65 tape-out requirements | GF180MCU PDK, KLayout | UMC65 foundry PDK, Siemens Calibre |
Capstone project phases
| Phase | Weeks | Activity | Project hrs |
|---|---|---|---|
| P1 | Wk 9–10 | Specification, architecture and topology selection; tile-area budget | 12 |
| P2 | Wk 10–11 | Hand calculations and behavioural model (Python / Verilog-A) | 12 |
| P3 | Wk 11–15 | Transistor-level design and schematic simulation across PVT and Monte Carlo | 40 |
| P4 | Wk 14–18 | Layout: floorplan within the tile, matching, guard rings, routing | 40 |
| P5 | Wk 18–21 | DRC/LVS clean, parasitic extraction and post-layout simulation across corners | 40 |
| P6 | Wk 21–23 | Mixed-signal integration, IO/ESD and pad connection, final signoff review | 30 |
| P7 | Wk 23–25 | Tape-out package: harness integration, pre-check, GDSII ready for VACS submission | 16 |
| P8 | Wk 25–26 | Final report, design review presentation and viva | 10 |
| Project total | 200 | ||
Example capstone projects
Interns work individually or in teams of two to three on one capstone design, sized to fit one or more VACS silicon tiles — 300 µm × 300 µm on GF180MCU or 200 µm × 200 µm on UMC65.
Bandgap reference + LDO regulator
A temperature-stable voltage reference driving a low-dropout regulator, characterised across PVT corners — the block every chip needs.
Two-stage op-amp / fully differential OTA
A compensated amplifier with common-mode feedback, designed by gm/Id and verified for gain, bandwidth, phase margin and noise after layout.
8-bit SAR ADC for sensor interfaces
A capacitive-DAC successive-approximation converter with comparator and digital SAR logic — the front end of edge-AI sensor nodes.
Charge-domain MAC for in-memory computing
An analog multiply-accumulate cell array that computes neural-network dot products in the charge domain at a fraction of digital energy.
Analog spiking neuron (LIF) circuit
A leaky-integrate-and-fire neuron with tunable leak and threshold, built from a handful of transistors for ultra-low-power inference.
Noise-based TRNG + temperature sensor
A true random number generator harvesting thermal noise / oscillator jitter, paired with an on-chip temperature sensor for tamper detection.
Note: The projects listed above are indicative only. Actual capstone projects may differ and are finalised with your mentor during the internship, based on your interests, mentor guidance and the silicon area available on the shuttle.
Skills you will build
- Size CMOS analog circuits with the gm/Id method
- Simulate DC, AC, transient, PVT and Monte Carlo
- Draw matched layouts: common-centroid, interdigitation, guard rings
- Clear DRC, LVS and antenna checks
- Extract parasitics and close post-layout performance
- Integrate analog blocks with digital control
Tools
The programme fee includes a validated open-source EDA environment and PDK. Every stage runs on open-source tools, with exposure to the commercial tools listed.
Tape-out through VACS
Your design, fabricated and packaged
The Vidyutt Academic Chip Shuttle (VACS) is Vidyutt's Design-to-Silicon programme. Designs that pass technical review are combined on a multi-project wafer, fabricated, packaged and returned for testing. Every intern — digital or analog — finishes with a tape-out-ready design; sending it to the fab is optional and is charged separately from the programme fee.
- 1Your design
- 2Verified design
- 3GDSII
- 4Signoff review
- 5VACS shuttle
- 6Fabrication
- 7Packaging
- 8Testing
- 9Your chip
Optional · paid separately
Tape-out cost for interns
| Technology node | Tile size | Tape-out cost per tile |
|---|---|---|
| GF180MCU | 300 µm × 300 µm | ₹35,000 |
| UMC65 | 200 µm × 200 µm | ₹35,000 |
The tape-out cost is borne by the intern (or shared by the project team) and is not part of the ₹50,000 programme fee. It covers signoff clearance, fabrication and packaging through VACS. Larger designs occupy multiple adjacent tiles, charged per tile.
When do I get my chip?
Fabrication and packaging continue after the internship ends. Interns are notified when packaged chips arrive and are invited to join post-silicon testing and bring-up.
Programme fee
₹50,000 per student — either track
Programme fee
₹50,000
per student · 6 months
Digital or Analog track
+ applicable taxes
Included in the fee
- All learning modules of your chosen track, with live sessions and recordings
- Guided lab exercises with a validated open-source EDA environment and PDK
- One-to-one mentorship and weekly design reviews
- Capstone design taken to a tape-out-ready GDSII
- Internship certificate and project completion letter
- Letter of recommendation for outstanding interns
Not included in the programme fee
VACS tape-out (fabrication and packaging) — optional, ₹35,000 per tile: 300 µm × 300 µm on GF180MCU or 200 µm × 200 µm on UMC65. See the Tape-out section.
Payment
| Item | Details |
|---|---|
| Optional tape-out | ₹35,000 per tile, paid separately |
Instalment options, payment mode and refund policy will be published here shortly.
Eligibility
Who should apply
Eligibility
- B.Tech / B.E. students in ECE, EEE, EIE, CSE or related branches
- Track A: a course in digital logic / digital electronics
- Track B: a course in analog electronics or network theory
- Basic programming in C or Python
- A laptop able to run Linux (8 GB RAM minimum, 16 GB recommended)
Format
- Duration: 6 months (26 weeks), about 17 hours per week
- Mode: Offline (on-site at Vidyutt) or Online with two campus immersions
- Limited seats in each track
- Last date to apply: 25 November 2026
- Selection results: 30 November 2026
- Internship starts: 10 December 2026
Mode of internship: travel and accommodation
| Mode | How it runs | Travel & accommodation |
|---|---|---|
| Offline (on-site) | Full internship at the Vidyutt campus | Students arrange their own accommodation and travel for the entire internship period. |
| Online | Live online sessions, with 2 campus immersions at Vidyutt | Students arrange their own accommodation and travel for both campus immersions. |
Accommodation and travel are not included in the ₹50,000 programme fee for either mode.
Deliverables
What you keep, whichever track you choose
- GDSII of your own design
- Simulation, verification and signoff reports
- Design files and scripts on Git
- VACS tape-out record, if you fabricate
- Internship certificate
- A portfolio for placements and higher studies
How to apply
Four steps to join
- 01
Apply online
Fill in the application form and choose your track — Digital VLSI or Analog & Mixed-Signal.
- 02
Screening test
A short online test matched to your track.
- 03
Interview
A technical conversation with a Vidyutt mentor from your track.
- 04
Enrol
Receive your offer letter, pay the fee and get access to the lab environment.
Important dates — December 2026 batch
- 25 Nov 2026Last date to apply
- 30 Nov 2026Selection results announced
- 10 Dec 2026Internship begins
The 26-week internship runs until June 2027.
Application form
Apply for the December 2026 batch
Choose your track and tell us about yourself in five short steps. Applications close on 25 November 2026.
Applications for the December 2026 batch are closed
The application deadline was 25 November 2026. For questions, or to hear about the next batch, write to info@vidyutt.com or call +91-9181189108.
Thank you, !
Your application for the Vidyutt 6-Month VLSI Internship — has been received. We will email you the screening-test details shortly. Selection results will be announced on 30 November 2026, and the internship starts on 10 December 2026. Keep an eye on , including your spam folder.
Your reference:
Questions? Write to info@vidyutt.com or call +91-9181189108.
FAQ
Frequently asked questions
Which track should I choose?
Choose Digital if you enjoy coding, logic design and computer architecture. Choose Analog & Mixed-Signal if you enjoy circuits, devices and analog electronics. Both lead to a tape-out-ready design and cost the same.
Do I need prior VLSI experience?
No. Track A starts from CMOS and Verilog fundamentals; Track B starts from MOS device characteristics and basic CMOS circuits.
Which tools will I use?
Track A: Icarus Verilog, Verilator, cocotb, Yosys, OpenSTA, OpenROAD / OpenLane, Magic, KLayout and Netgen. Track B: Xschem, ngspice, Magic, Netgen and KLayout. Both use the GF180MCU process design kit, with exposure to the commercial tools listed in each track.
Is fabrication included in the ₹50,000 fee?
No. Every intern completes a tape-out-ready design. Fabricating it through VACS is optional and costs ₹35,000 per tile — 300 µm × 300 µm on GF180MCU or 200 µm × 200 µm on UMC65 — paid separately by the intern or project team.
Will my design really be fabricated?
If you opt for tape-out, designs that pass technical review are submitted through the Vidyutt Academic Chip Shuttle (VACS). Fabrication and packaging continue after the internship, and packaged chips are returned for testing.
Is accommodation or travel provided?
No. In offline mode, students arrange their own accommodation and travel for the entire internship period. In online mode, there are 2 campus immersions, and students arrange their own accommodation and travel for these visits.
Are the listed capstone projects fixed?
No. The projects shown are indicative only. Your actual capstone project is finalised with your mentor during the internship and may differ from the examples.
Can I do this alongside my college semester?
The schedule is about 17 hours per week, designed to fit alongside coursework.
Can I count this as my college internship or major project?
Vidyutt provides an internship certificate and completion letter. Check your institution's requirements.
Is this a stipend internship?
No. This is a fee-based training internship; the ₹50,000 programme fee covers training, mentorship and lab access. Optional tape-out is charged separately.
Design it. Sign it off. Hold it in your hand.
Apply for the Vidyutt 6-Month VLSI Design & Tape-out Internship — Digital or Analog track.
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