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Vidyutt Academic Chip Shuttle · VACS

India's Design-to-Silicon Initiative.
Chip for All.

A Design-to-Silicon program that lets universities, research labs, startups, MSMEs, and VLSI enthusiasts transform digital designs into fabricated and packaged integrated circuits – affordably.

Design. Fabricate. Deploy.
Estimate Your Cost Request a Quotation
Chip for All
Democratizing silicon access
From ₹25,000
Affordable service tracks
MPW Fabrication
TSMC · GF · UMC · IHP
5 Packaged ICs
Per participating institution
Program Overview

Democratizing Semiconductor Innovation

The Vidyutt Academic Chip Shuttle (VACS) is a unique Design-to-Silicon initiative that enables universities, research laboratories, startups, MSMEs, semiconductor professionals, VLSI enthusiasts and hobbyists to transform digital designs into fabricated and packaged integrated circuits.

It provides access to industry-standard design methodologies, implementation expertise, fabrication support, packaging services, and post-silicon testing through both commercial and Open Source EDA ecosystems – making custom silicon development accessible, affordable, and educational.

Why VACS?

Most academic projects stop at simulation or FPGA validation due to the cost and complexity of ASIC realization. VACS bridges that gap.

ASIC implementation expertise
Access to advanced technology nodes
Fabrication and packaging support
Industry-standard design methodologies
Hands-on silicon realization experience
Faculty and student skill development
Free live master classes with IIT & international faculty and industry experts
3-month to 1-year research internships at IITs / NITs / IIITs
Research publication opportunities on fabricated silicon with IIT faculty, plus startup prototyping
Program Eligibility

Who Can Participate

Intended for
•National & International Academic Institutes / Universities
•Research Laboratories
Can also be extended to
•Government Organizations
•Startups and MSMEs
•Semiconductor Professionals
•VLSI Enthusiasts and Hobbyists
Participation Requirements

Shuttle Criteria

›Minimum 5 designs per participating university or institution
›Each design occupies a minimum tile of 200 µm × 200 µm on silicon
›Larger designs may occupy multiple adjacent tiles with larger IOs
›Maximum 6 IOs per design per 200 µm × 200 µm tile
›Each institution receives 5 packaged ICs for testing and evaluation
›Synthesizable RTL must be provided by the participants
›Participants support the technical implementation whenever required

VACS Service Tracks

Choose a complete turnkey implementation or expert-guided mentorship – with commercial or Open Source EDA flows.

Turnkey · Commercial

Turnkey Commercial

End-to-end ASIC implementation using industry-standard commercial EDA tools.

₹50,000
per design · up to 2 tiles
✓PDK Introduction Workshop
✓Design Feasibility Review
✓RTL Synthesis & Complete PnR
✓Timing Closure & Physical Verification
✓GDSII Generation
✓Fabrication & Packaging Coordination
For universities, research labs & startups seeking complete turnkey execution.
Most Affordable
Turnkey · Open Source Silicon

Turnkey Open Source Silicon

End-to-end ASIC implementation using modern Open Source EDA methodologies.

₹30,000
per design · up to 2 tiles
✓Open Source PDK Introduction
✓Design Review
✓RTL-to-GDSII Implementation
✓Signoff Checks
✓GDSII Generation
✓Fabrication & Packaging Support
For educational institutions & startups seeking affordable silicon realization.
Mentorship · Commercial EDA

Mentorship (Commercial EDA)

Expert-guided ASIC implementation for teams with their own commercial EDA tools.

₹35,000
includes 10 hours of expert support
✓4-Hour PDK & Flow Training
✓Up to 10 Hours Expert Support
✓Design Reviews & Physical Design Guidance
✓Timing Closure & Signoff Support
✓Implementation Debugging
✓2 Hours Weekly Consultation
For institutions with commercial EDA licenses and implementation teams.
Mentorship · Open Source EDA

Mentorship (Open Source EDA)

Expert-guided ASIC implementation using OpenROAD-based Open Source flows.

₹25,000
includes 10 hours of expert support
✓4-Hour Open Source Flow Training
✓Up to 10 Hours Expert Support
✓Design Reviews & Flow Setup Assistance
✓Physical Design Guidance
✓Signoff Preparation
✓Weekly Technical Consultation
For budget-conscious institutions building in-house ASIC capability.
Fabrication · Tapeout Only

Tapeout Only

Silicon fabrication for teams who bring an implementation-ready GDSII — signoff clearance and MPW fabrication through VACS.

₹20,000
per tile · signoff auto-added
✓Design Submission Review
✓Signoff Clearance (DRC, LVS, STA)
✓GDSII Acceptance & MPW Participation
✓Foundry Coordination
✓Packaging & Silicon Delivery
✓Optional Testing Support
For experienced teams with an implementation-ready GDSII seeking fabrication access.
Estimate Your Total Cost
Pricing is indicative and subject to confirmation – request a detailed quotation for your specific design.
Fabrication & Packaging

MPW Fabrication Programs

After successful implementation and signoff, designs are submitted for fabrication through supported Multi-Project Wafer (MPW) programs run by leading foundries.

TSMC MPW
GlobalFoundries MPW
UMC MPW
IHP
Additional foundry programs (subject to availability)
Silicon Tile Pricing
₹15,000
per tile · 200 µm × 200 µm silicon area
Package includes
✓Wafer Fabrication
✓Packaging
✓Delivery of Packaged Devices
Larger designs may occupy multiple tiles based on area requirements. Fabrication charges also apply to the mentorship tracks, with a minimum of 1 tile required per design. The Tapeout Only track is billed at ₹20,000 per tile.
Additional Support Plans
₹15,000
Additional Expert Support – 3 consultation hours
₹10,000
RTL Readiness Review
₹20,000
Design Signoff Review
On Request
Silicon Bring-up Support
One RTL Readiness Review (₹10,000) is included on the four implementation tracks; the mentorship tracks also include one Design Signoff Review. The Tapeout Only track has no RTL review — one Design Signoff Review (₹20,000) is auto-added for every three tiles.

Deliverables

Depending on the selected track, participants may receive:

•Design Implementation Reports
•Timing Reports
•Area Reports
•Power Reports
•Physical Verification Reports
•GDSII Database
•Fabrication & Packaging Support
•Packaged Silicon Samples
•Training Material
•Technical Consultation

Training & Knowledge Transfer

VACS builds semiconductor expertise towards self-reliance for Viksit Bharat 2047. Modules include:

▸Introduction to ASIC Design Flow
▸Physical Design Fundamentals
▸OpenROAD / OpenLane Flow
▸Commercial EDA Tool Flow
▸Timing Closure Techniques
▸Design for Testability (DFT)
▸Signoff Methodologies
▸Tapeout Readiness
▸Silicon Bring-Up Fundamentals
VACS Vision · Chip for All

Empowering India's Semiconductor Revolution

Affordable access to silicon realization for students, researchers, startups, MSMEs, and professionals – fostering indigenous innovation for Atmanirbhar Bharat and Viksit Bharat 2047. From RTL to Real Silicon.

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