Fabricating a chip has a reputation for being extraordinarily expensive — and a full production run is. But there is a well-established path that puts real silicon within reach of a university lab or an early-stage startup: the Multi-Project Wafer, or MPW.
The problem: masks are expensive
To manufacture a chip, the foundry needs a set of photomasks — the stencils that define every layer of the design. A full mask set for an advanced node can cost a fortune, and that cost is the same whether you make one wafer or ten thousand. For a single research design, it is simply not viable.
The idea: share the wafer
An MPW shuttle solves this by placing many independent designs from different teams onto a single wafer, sharing one mask set. The cost is split across all participants, so each team pays only for the silicon area it uses.
Think of it as a shared bus to the foundry: you buy a seat, not the whole vehicle.
What you get back
After fabrication and dicing, each participant receives a small number of packaged chips of their own design — enough to bring up, measure, and validate in the lab.
- A handful of packaged devices per design
- Real silicon behaviour to compare against simulation
- A tangible result to publish, demo, or build a product around
Tiles and area
Because you pay for area, MPW programs typically sell silicon in tiles — a fixed unit such as 200 µm × 200 µm. A small design fits in one tile; a larger one spans several adjacent tiles.
| Design size | Tiles | Typical use |
|---|---|---|
| Small IP block | 1 | Student project, single accelerator |
| Medium subsystem | 2–4 | Research prototype |
| Large SoC-lite | 6–9 | Multi-block demonstrator |
MPW in the VACS program
The VACS — Vidyutt Academic Chip Shuttle is built around exactly this model. We coordinate implementation, signoff, and submission to supported MPW programs, then handle packaging and delivery — so your team can focus on the design, not the logistics.
Curious what your design would cost? Try the VACS Cost Estimator, or request a quotation.