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Physical Design & Signoff

DRC and LVS: What They Check and Why They Matter

Design Rule Checking (DRC) and Layout vs. Schematic (LVS) are two of the most fundamental signoff checks in chip design – every chip must pass both before it can be sent to manufacturing.

VIDYUTT• July 31, 2026• 2 min read
Figure 1: Design Rule Check verifies manufacturability; Layout vs. Schematic verifies the layout matches the intended design.
Figure 1: Design Rule Check verifies manufacturability; Layout vs. Schematic verifies the layout matches the intended design.

What DRC and LVS Involve

DRC verifies that every shape in the physical layout obeys the foundry's geometric rules – minimum spacing, minimum widths, and hundreds of other constraints that ensure the design can actually be manufactured reliably on a given process. LVS takes a different approach: it extracts a netlist directly from the physical layout and compares it against the intended schematic/netlist, catching any place where the layout doesn't actually implement the circuit it was supposed to.

Why It Matters

A DRC violation can mean a manufacturing defect or reliability failure; an LVS mismatch can mean the chip simply won't function as designed, even if it's perfectly manufacturable. Foundries typically require a fully clean DRC and LVS report before accepting a design for fabrication, making these two checks a hard gate on every tape-out.

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