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PD & Signoff
End-to-end RTL-to-GDSII implementation – synthesis, floorplanning, clock tree synthesis and DFM, through power planning, IR drop, electromigration, timing signoff and the DRC/LVS checklist that stands between you and the foundry.
10 articles
RTL-to-GDSII Implementation Design for Manufacturability (DFM): Improving Yield Beyond the Rules Passing basic design rule checks is necessary but not always sufficient to guarantee good manufacturing yield. Design for Manufacturability (DFM) goes a step further, applying additional techniques that improve yield even within rule-compliant layouts.
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Physical Design & Signoff Timing Signoff Across Corners: Why One Timing Run Isn't Enough A chip that meets timing under perfect, average manufacturing conditions can still fail in the real world, where every chip comes off the manufacturing line with slightly different transistor characteristics, and operates across a range of voltages and temperatures.
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Physical Design & Signoff Tape-Out Readiness: The Final Checklist Before Manufacturing Tape-out is the point of no return – once a design is submitted to the foundry, changes require an expensive and time-consuming re-spin. A rigorous, comprehensive readiness checklist is the final safeguard before this irreversible step.
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Physical Design & Signoff DRC and LVS: What They Check and Why They Matter Design Rule Checking (DRC) and Layout vs. Schematic (LVS) are two of the most fundamental signoff checks in chip design – every chip must pass both before it can be sent to manufacturing.
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Physical Design & Signoff Electromigration (EM) and Reliability Signoff Electromigration is a physical phenomenon where sustained high current density in a metal wire gradually causes atoms to migrate, eventually leading to open circuits or shorts. EM signoff ensures a chip will remain reliable over its intended operating lifetime.
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RTL-to-GDSII Implementation Clock Tree Synthesis (CTS) Explained Clock Tree Synthesis builds the network of buffers and wires that distributes a chip's clock signal from its source to every single flip-flop on the die – often hundreds of thousands of them – while keeping timing skew within tight bounds.
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RTL-to-GDSII Implementation Logic Synthesis Fundamentals: From RTL to Gates Logic synthesis is the automated process that converts RTL code into a gate-level netlist built from a specific manufacturing technology's standard cells. It's the first major step in turning a design description into something that can actually be built.
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RTL-to-GDSII Implementation Static Timing Analysis (STA) Fundamentals Static Timing Analysis is the exhaustive method used to verify that every timing path in a chip meets its requirements – without needing to simulate a single test vector. It's one of the most fundamental and universally-used techniques in digital design signoff.
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Physical Design & Signoff Power Planning and IR Drop Analysis Delivering clean, stable power to every part of a chip is deceptively difficult at modern scale. Power planning designs the on-chip network that distributes power, and IR drop analysis verifies that network actually delivers sufficient voltage everywhere it's needed.
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RTL-to-GDSII Implementation Floorplanning Basics: Deciding Where Everything Goes Floorplanning is the process of deciding the physical placement of major blocks on a chip – cores, memories, I/O, and power structures – before detailed placement and routing begin. It's one of the most consequential decisions in the entire implementation flow.
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