What EM and Reliability Signoff Involve
Every wire and via in the design carries some amount of current, determined by the switching activity of the logic it connects. EM analysis calculates the current density in each of these interconnects and compares it against the foundry's maximum allowed current density for a given wire width and expected lifetime. Wires exceeding these limits are widened, or the logic driving them is adjusted, to bring current density back within safe bounds.
Why It Matters
Electromigration failures don't necessarily show up immediately – a chip might work perfectly at first, then fail months or years into its operational life as wires gradually degrade. This makes EM signoff essential for any product with a meaningful reliability requirement, since failures caused by it are effectively invisible during initial testing.